Keywords
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| Fuzzy logic, Micro Grid, MPPT, pulse widthmodulation PWM),photovoltaic(PV) system,and THD |
INTRODUCTION
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1.1 MULTILEVEL INVERTOR
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| Multilevel inverter technology has emerged recently as a very important alternative in the area of high-power medium-voltage energy control. The popular methods are diode-clamped inverter (neutral-point clamped), capacitorclamped (flying capacitor), and cascaded multilevel inverters with separate DC sources. The last one is most fusible topology used in all areas. This paper presents the most relevant structure of the multilevel inverter using cascadedinverters with separated dc sources will be introduced, as well as switching pattern. |
1.1.1 Full-bridge or “H-bridge” Voltage Source Inverter
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| The smallest number of voltage levels for a multilevel inverter using cascaded-inverter with SDCSs is three. To achieve a three-level waveform, a single full-bridge inverter is employed. Basically, a full-bridge inverter is known as an H-bridge cell, which is illustrated in Fig. 1. The inverter circuit consists of four main switches and four freewheeling diodes. |
1.2 CASCADED H-BRIDGES INVERTER
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| A single-phase structure of an m-level cascaded inverter is illustrated in Figure 1.Each separate dc source (SDCS) is connected to a single-phase H-bridge, inverter. Each inverter level can generate three different voltage outputs, +Vdc, 0, and –Vdc by connecting the dc source to the ac output by different combinations of the four switches, |
 (1.1) |
| S1, S2, S3, and S4. To obtain +Vdc, switches S1 and S4 are turned on, whereas –Vdc can be obtained by turning on switches S2 and S3. By turning on S1 and S2 or S3 and S4, the output voltage is 0. The ac outputs of each of the different full-bridge inverter levels are connected in series such that the synthesized voltage waveform is the sum of the inverter outputs. The number of output phase voltage levels m in a cascade inverter is defined by |
| m = 2s+1, |
| Where‘s’ is the number of separate dc sources. |
| An example phase voltage waveform for an m-level cascaded H-bridge inverter with S-SDCSs and S full bridges is shown in Figure 2 |
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CONVENTIONAL MULTYLEVAL H- BRIDGE TOPOLOGY
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| The proposed single-phase seven-level inverter was developed from the five-level inverter. It comprises a single-phase conventional H-bridge inverter, two bidirectional switches, and a capacitor voltage divider formed by C1, C2,and C3, as shown in Fig. 3. The modified H-bridge topology is significantly advantageous over other topologies, i.e., less power switch, power diodes, and less capacitors for inverters of the same number of levels. Photovoltaic (PV) arrays were connected to the inverter via a dc–dc boost converter. The power generated by the inverter is to be delivered to the power network, so the utility grid, rather than a load, was used. The dc–dc boost converter was required because the PV arrays had a voltage that was lower than the grid voltage. High dc bus voltages are necessary to ensure that power flows from the PV arrays to the grid. A filtering inductance Lf was used to filter the current injected into the grid. Proper switching of the inverter can produce seven output-voltage levels (Vdc, 2Vdc/3, Vdc/3, 0,−Vdc,−2Vdc/3,−Vdc/3) from the dc supply voltage. The proposed inverter’s operation can be divided into seven switching states, as shown in Fig. 4(a)–(g). Fig. 4(a), (d),and (g) shows a conventional inverter’s operational states in sequence, while Fig. 4(b), (c), (e), and (f) shows additional states in the proposed inverter synthesizing one- and twothird levels of the dc-bus voltage. The required seven levels of output voltage were generated as follows. |
| 1) Maximum positive output (Vdc): S1 is ON, connecting the load positive terminal to Vd, And S4 is ON, connecting the load negative terminal to ground. All other controlled switches are OFF; the voltage applied to the load terminals is Vdc. Fig. 4(a) shows the current paths that are active at this stage. |
| 2) Two-third positive output (2Vdc/3): The bidirectional switch S5 is ON, connecting the load positive terminal and S4 is ON, connecting the load negative terminal to ground.All other controlled switches are OFF; the voltage applied to the load terminals is 2Vdc/3. Fig. 4(b)shows the current paths that are active at this stage. |
| 3) One-third positive output (Vdc/3): The bidirectional switch S6 is ON, connecting the load positive terminal, and S4 is ON, connecting the load negative terminal to ground. All other controlled switches are OFF; the voltage applied to the load terminals is Vdc/3. Fig. 4(c) shows the current paths that are active at this stage. |
| 4) Zero output: This level can be produced by two switching combinations; switches S3 and S4 are ON, or S1 and S2 are ON, and all other controlled switches are OFF; terminal ab is a short circuit, and the voltage applied to the load terminals is zero. Fig. 4(d) shows the current paths that are active at this stage. |
| 5) One-third negative output (−Vdc/3): The bidirectional switch S5 is ON, connecting the load positive terminal, and S2 is ON, connecting the load negative terminal to Vdc. All other controlled switches are OFF; the voltage applied to the load terminals is −Vdc/3. Fig. 4(e) shows the current paths that are active at this stage. |
| 6) Two-third negative output (−2Vdc/3): The bidirectional switch S6 is ON, connecting the load positive terminal, and S2 is ON, connecting the load negative terminal to ground. All other controlled switches are OFF; the voltage applied to the load terminals is −2Vdc/3. Fig. 4(f) shows the current paths that are active at this stage. |
| 7) Maximum negative output (−Vdc): S2 is ON, connecting the load negative terminal to Vdc, and S3 is ON, connecting the load positive terminal to ground. All other controlled switches are OFF; the voltage applied to the load terminals is −Vdc. Fig. 4(g) shows the current paths that are active at this stage. |
2.1 PWM Modulation
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| A novel PWM modulation technique was introduced to generate the PWM switching signals. Three reference signals (Vref1, Vref2, and Vref3) were compared with a carrier signal (Vcarrier). The reference signals had the same frequency and amplitude and were in phase with an offset value that was equivalent to the amplitude of the carrier signal. The reference signals were each compared with the carrier signal. If Vref1 had exceeded the peak amplitude of Vcarrier, Vref2 was compared with Vcarrier until it had exceeded the peak amplitude of Vcarrier. Then, onward, Vref3 would take charge and would be compared with Vcarrier until it reached zero. Once Vref3 had reached zero, Vref2 would be compared until it reached zero. Then, onward, Vref1 would be compared with Vcarrier. Fig. 3 shows the resulting switching pattern. Switches S1, S3, S5, and S6 would be switching at the rate of the carrier signal frequency, whereas S2 and S4 would operate at a frequency that was equivalent to the fundamental frequency. |
| The phase angle depends on modulation index Ma. Theoretically for a single reference signal and a single carrier signal, the modulation index is defined to be |
| Ma = Am/Ac (02) |
| while for a single-reference signal and a dual carrier signal, the modulation index is defined to be |
| Ma = Am/2Ac. (03) |
| Since the proposed seven-level PWM inverter utilizes three carrier signals, the modulation index is defined to be |
| Ma = Am/3Ac (04) |
| where Ac is the peak-to-peak value of the carrier signal and Am is the peak value of the voltage reference signal Vref . When the modulation index is less than 0.33, the phase angle displacement is |
| θ1 =θ2 = θ3 = θ4 = π/2 (05) |
| θ5 =θ6 = θ7 = θ8 =3π/2 . (06) |
| For one cycle of the fundamental frequency, the proposed inverter operated through six modes. Fig. 6 shows the per unit output-voltage signal for one cycle. The six modes are described as follows: |
| Mode 1 : 0 < ωt < θ1 and θ4 < ωt < π |
| Mode 2 : θ1 < ωt < θ2 and θ3 < ωt < θ4 |
| Mode 3 : θ2 < ωt < θ3 |
| Mode 4 : π < ωt < θ5 and θ8 < ωt < 2π |
| Mode 5 : θ5 < ωt < θ6 and θ7 < ωt < θ8 |
| Mode 6 : θ6 < ωt < θ7. |
| On the other hand, when the modulation index is more than 0.33 and less than 0.66, the phase angle displacement is determined by |
| θ1 = sin−1(Ac/Am) (07) |
| θ2 =θ3 = π2 (08) |
| θ4 =π − θ1 (09) |
| θ5 =π + θ1 (10) |
| θ6 =θ7 =3π/2 (11) |
| θ8 =2π − θ1. (12) |
| If the modulation index is more than 0.66, the phase angle displacement is determined by |
| θ1 = sin−1(Ac/Am) (13) |
| θ2 = sin−1(2Ac/Am) (14) |
| θ3 =π − θ2 (15) |
| θ4 =π − θ1 (16) |
| θ5 =π + θ1 (17) |
| θ6 =π + θ2 (18) |
| θ7 =2π − θ2 (19) |
| θ8 =2π − θ1. (20) |
| For Ma that is equal to, or less than, 0.33, only the lower reference wave (Vref3) is compared with the triangular carrier signal. The inverter’s behavior is similar to that of a conventional full-bridge three-level PWM inverter. However, if Ma is more than 0.33 and less than 0.66, only Vref2 and Vref3 reference signals are compared with the triangular carrier wave. The output voltage consists of five dc-voltage levels. The modulation index is set to be more than 0.66 for seven levels of output voltage to be produced. Three reference signals have to be compared with the triangular carrier signal to produce switching signals for the switches. |
PROPOSED MULTY LEVAL INVERTER TOPOLOGY
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| In proposed system the out put of the multilevel inverter is improved with help of advanced controller i.e FUZZY Logic controller. |
3.1) Fuzzy logic:
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| In recent years, the number and variety of applications of fuzzy logic have increased significantly. There are five primary GUI tools for building, editing, and observing fuzzy inference systems in the Fuzzy Logic Toolbox. The Fuzzy Inference System or FIS Editor, the Membership Function Editor, the Rule Editor, the Rule Viewer, and the Surface Viewer. the fuzzy controller membership function and its surface view is shown in below fig.7&8. |
3.2 ) Proposed simulated circuit:
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3.3 ) Proposed FUZZY controller Circuit
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COMPARISON of MATLAB /SIMULATION RESULTS
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| MATLAB SIMULINK simulated the proposed configuration before it was physically implemented in a prototype. The PWM switching patterns were generated by comparing three reference signals (Vref1, Vref2, and Vref3) against a triangular carrier signal (see Fig. 6). |
| Subsequently, the comparing process produced PWM switching signals for switches S1–S6, as Figs. 7–9 show. One leg of the inverter operated at a high switching rate that was equivalent to the frequency of the carrier signal, while the other leg operated at the rate of the fundamental frequency (i.e., 50 Hz). Switches S5 and S6 also operated at the rate of the carrier signal. Fig. 10. Inverter output voltage (Vinv). Fig. 11. Grid voltage (Vgrid) and grid current (Igrid).of the carrier signal. Fig. 10 shows the simulation result of inverter output voltage Vinv. The dc-bus voltage was set at 300 V (>√2Vgrid; in this case, Vgrid was 120 V). The dc-bus voltage must always be higher than √2 of Vgrid to inject current into the grid, or current will be injected from the grid into the inverter. Therefore, operation is recommended to be between Ma = 0.66 and Ma = 1.0. Vinv comprises seven voltage levels, namely, Vdc, 2Vdc/3, Vdc/3, 0, −Vdc, −2Vdc/3, and −Vdc/3.The current flowing into the grid was filtered to resemble a pure sine wave in phase with the grid voltage see Fig. 11). As Igrid is almost a pure sine wave at unity power factor, the total harmonic distortion (THD) can be reduced compared with the THD. |
MULTILEVEL INVERTER SPECIFICATIONS AND CONTROLLER PARAMETERS.
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| The below table depicts the specifications and parameters of the inverter |
CONCLUSION
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| 7 level Multilevel inverters offer improved output waveforms and lower THD. This paper has presented a novel PWM switching scheme for the proposed multilevel inverter. It utilizes three reference signals and a triangular carrier signal to generate PWM switching signals. The behavior of the proposed multilevel inverter was analyzed in detail. A FUZZY control is implemented to optimize the performance of the inverter. By controlling the modulation index, the desired number of levels of the inverter’s output voltage can be achieved. The less THD in the seven-level inverter compared with that in the five- and three-level inverters is an attractive solution for grid-connected PV inverters. |
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Tables at a glance
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Figures at a glance
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Figure 10 |
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Figure 12 |
Figure 13 |
Figure 14 |
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