International Journal of Advanced Research in Electrical, Electronics and Instrumentation Engineering

International Journal of Advanced Research in Electrical, Electronics and Instrumentation Engineering

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Delay Locked Loop Using Glitch Free Nand- Based DCDL

S.Kokilamani1, K.R.Nimisha2
  1. PG Scholar, Dept. of ECE, Sri Eshwar College of Engineering, Coimbatore, Tamilnadu, India 1
  2. Assistant professor, Dept. of ECE, Sri Eshwar College of Engineering, Coimbatore, Tamilnadu, India 2
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Abstract

A delay locked loop (DLL) is used to synchronize the external and internal clock. This is used to reduce the clock-deskew problem. The main block in DLL is delay line. Digitally controlled delay lines (DCDL) exhibits a glitching problem. This glitching problem is reduced by using NAND-Based DCDL. Sense amplifier based driving circuit is used to control the control bits in DCDL. The proposed DCDL is adopted in the DLL in order to reduce the power and delay time.

Keywords
DLL, PLL, Phase comparator, DCDL and Shift register.

INTRODUCTION
In electronics, a delay-locked loop (DLL) is a digital circuit similar to a phase-locked loop (PLL), but internal voltagecontrolled oscillator is not present in the DLL as like PLL. The clock rise-to-data output valid timing characteristic of integrated circuit is enhanced by DLL. DLL is also used for clock recovery (CDR). A DLL can be seen as a negativedelay gate placed in the clock path of a digital circuit. The main key block of a DLL is a delay chain. DLL provides high-bandwidth data transmission rates between devices. DLL transmissions doesn’t have low clock skew between output clock signals, propagation delay and advanced clock domain control. A DLL is fed by a reference clock. A DLL tries to determine the period of that reference clock by adjusting a feedback look via the delay line. The loop is considered locked when the delayed clock signal matches the incoming clock signal.
Reducing the clock skew can not only further increase system clock frequency but also avoid system malfunction. Phase-locked loops (PLL’s) and delay-locked loops (DLL’s) have been widely adopted to solve the clock-skew problem. Such kinds of circuits are called clock-deskew buffers. A DLL consists of a phase detector (PD) or a phase comparator (PC), a variable delay line, and a shift register to convert the PD’s output signal to a control signal for the delay line. It detects the phase error between the input clock and its output clock and automatically tunes the delay line to insert an optimal delay time between them for clock synchronization.

EXISTING DLL
The DLL has delay line, phase comparator and shift register as the components. Figure.1 shows the block diagram of the register-controlled DLL (RDLL). The feedback clock signal is the delayed version of the input clock signal, and the shift register controls the amount of the delay time. The PC compares the phases of the input clock signal and the output clock signal. The output of the PC is used to control the shift register. The input clock signal is a common input for every delay stage.
At any time, only one bit of the shift register is active to select a point of entry of the delay line for the input clock signal. The number of the delay stages which the input clock signal goes through determines total amount of delay. Under this circumstance, the loop is locked and will not alter until the phase error exceeds the unit delay again. The resolution of the RDLL is determined by the unit delay of the delay line and the total delay time of the delay line determines the DLL’s deskew range and the lowest operation frequency. Wider deskew range or lower operation frequency can be achieved by adding more delay stages in the delay line.
A phase detector or phase comparator is a logic gate that generates a voltage signal which represents the difference in phase between two signal inputs. It is an essential element of the phase-locked loop (PLL). Detecting phase difference is very important in many applications, such as radar and telecommunication systems, servo mechanisms, and demodulators.

A.DLL WITH GLITCH FREE NAND-BASED DCDL
In the glitching DCDL circuit [8], only one control bit is used. When there is a sudden switching takes place in the control bit, glitches are generated. Figure 2 represents DLL with glitch free NAND-Based DCDL.
Figure 3 represents the glitch free NAND-Based DCDL. This uses two control bits Si and Ti. In this figure “A” denotes the fast input of each NAND gate. Gates marked with “D” represents dummy cells added for load balancing. When Si=0 and Ti=1 the NAND “3” output is equal to 1 and the NAND “4” allows the signal propagation in the lower NAND gates chain. And if Si=1 and Ti=1, the state is turn state. In this state the upper input of the DE is passed to the output of NAND “3”. If Si=1 and Ti=0 the state is post-turn state. In this DE the output of the NAND “4” is stuck-at 1, by allowing the propagation, in the previous DE (which is in turn-state), of the output of NAND “3” through NAND “4”. The circuit of figure.3 is an inverting DCDL. In this circuit the first DE is never in post-turn state, therefore T0 is always 1.

B.DRIVING CIRCUIT
Driving circuit can be used to generate the control-bits of the DCDL. By analysing, it can be noted that Si signals have to be delayed with respect to Ti signals and that it could be useful to have a different delay for LH and HL transitions. The existing DCDL uses dual edge triggered flip-flop as the driving circuit. This consumes more power. When this is adopted in the DLL, this power consumption is also high. In figure 4 driving circuit is shown with DCDL.

PROPOSED DLL

A.DLL WITH PROPOSED GLITCH FREE NAND-BASED DCDL
Proposed DLL uses proposed glitch free DCDL .by using this DLL power and delay time is reduced.

B.PROPOSED DCDL
Proposed DCDL uses dual edge triggered sense amplifier flip-flop as a driving circuit. This is shown in figure 6. By using this proposed driving circuit, the power and delay time of existing glitch free NAND-Based DCDL is reduced. The sense amplifier based dual triggered flip-flop in figure 6 consists of three stages. Those are pulse generating, sensing and latching stages. First stage is used to generate the pulses, second stage is used to sense the pulses and third stage is used to produce the output during the rising and falling edges.

SIMULATION RESULTS AND DISCUSSION

1. DLL with Glitching NAND-Based DCDL
The above figure shows that DLL with glitching NAND-Based DCDL.

2. Simulation Result of DLL with existing glitch free DCDL
The figure.8 shows that Delay Locked Loop with existing glitch free NAND-Based DCDL.

3. Simulation Result of DLL with Proposed Glitch Free NAND-Based DCDL
The figure.9 shows that simulation of DLL with Proposed Glitch Free NAND-Based DCDL.

4. Existing DLL Power Analysis

5. Proposed DLL Power Analysis

5. Delay Time Analysis of Existing DLL

6. Delay Time Analysis of Proposed DLL

COMPARISON OF POWER AND AREA
Comparison Chart for Power
Comparison Chart for Delay Time

CONCLUSION
A Delay Locked Loop with glitch free NAND-Based DCDL has been presented. Digitally Controlled Delay Lines plays an important role in DLL and the drawback is glitches. A NAND-based DCDL is used to reduce the glitches with dual edge triggered sense amplifier flip-flop as driving circuit. The DCDL circuit consumes low power. The DLL uses the proposed DCDL circuit in order to reduce the power, area and delay time. The comparison of existing and proposed DLL has been presented. The output is shown by using FPGA kit. The simulation results confirm the correctness of developed model and show that proposed solutions improve the resolution with respect to previous approaches.

Figures at a glance
Figure 1 Figure 2 Figure 3 Figure 4 Figure 5
Figure 1 Figure 2 Figure 3 Figure 4 Figure 5
Figure 1 Figure 2 Figure 3 Figure 4 Figure 5
Figure 6 Figure 7 Figure 8 Figure 9 Figure 10
Figure 1 Figure 2 Figure 3 Figure 4 Figure 5
Figure 11 Figure 12 Figure 13 Figure 14 Figure 15
 

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