Efficient Design of MAC Hybrid Adder in
Quantum-Dot Cellular Automata

Bhuvaneswaran M; Shankar N.K.

Efficient Design of MAC Hybrid Adder in Quantum-Dot Cellular Automata

Bhuvaneswaran M¹, Shankar N.K.²

ME Student [VLSI Design], Dept.of ECE, Muthayammal Engineering College, Rasipuram, Tamilnadu, India
Asst.Professor, Dept of ECE, Muthayammal Engineering College, Rasipuram, Tamilnadu, India

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Abstract

Minimizing area and power is the more challenging task in modern VLSI design. Adders are the most widely used components in many circuits. The design of area and power efficient high-speed data path logic systems forms the largest areas of research in VLSI system design. Several types of adders are available in practice, each type is used for particular purpose based on their performance and features. In this project, design an efficient hybrid adder that combines the Ladner–Fischer adder with a ripple carry adder. And show that the hybrid adder has better performance (in terms of latency) in Quantum-dot cellular automata (QCA) than a Ladner–Fischer or a ripple carry adder. In proposed, design MAC (multiply accumulate) hybrid adder , the circuit is operational to perform a MAC (multiply accumulate) operation and to perform a multiply operation without interfacing with the accumulate value of MAC operation using Quantum-dot cellular automata (QCA). And Compare the area and power with existing adders.

Keywords

Majority Gates, Quantum-dot Cellular Automata,. Multiply Accumulate, Hybrid Adder.

INTRODUCTION

A.Quantum-dot Cellular Automata(QCA)

CMOS technology has experienced serious problems such as short channel effects, doping fluctuations, increasingly difficult and expensive lithography at nano scale, high leakage current and speed limitation in GHz range. Many alternative technologies have been introduced in the Industry Technology Roadmap for Semiconductors (ITRS). A Quantum-dot cellular automaton (QCA) is one of these promising nanotechnologies that could be utilized instead of conventional transistor technology in the future. Quantumdot Cellular Automata provides new possibilities to achieve outstanding properties such as extremely high density and fast operation speed at Tera Hertz frequencies together with low power dissipation .

QCA circuits are implemented with two principle gates: majority and inverter gates. As the basic element in QCA is majority gate, the structure of this gate is a significant factor in designing circuits in QCA. The basic element of QCA is a cell. A QCA cell, shown in Fig 1, due to the Columbic interactions consists of four quantum dots at the corners of a square with two extra mobile electrons in two different configurations, thus we have two polarizations ( p= +1 ,p= -1) used for encoding binary information. Quantum Cellular Automata(QCA) is a structure made up of identical cells realized though a variety of technologies such as electrodynamic, ferromagnetic and molecular. Molecular QCA is particularly attractive because of its projected density of 1x1012 devices/cm2 and switching speeds in the THz range.The Columbic interactions between two neighbour cells cause these cells to have the same polarizations. Therefore a series of QCA cells performs as wire in QCA.

B. Three Input Majority Gate

The principle QCA logical circuits are majority and inverter gates. The Basic QCA Cell and two possible polarizations and corresponding QCA wire is shown in figure 1 and figure 2 respectively. Fig 3 demonstrates two different inverter gates.

Up to now, most circuits have been implemented by three majority gate that act based on Eq. (1) and its corresponding QCA as well as symbol is shown below in figure 4.

QCA promises to provide the highest device density with low power consumption and high switching speeds. In addition,QCA uses the same technology to build both the logic gates and the wires carrying logic signals.

EXISTING METHOD

A.QCA Design of Ladner–Fischer Adder

The prefix graph of a 16-bit ladner–fischer adder (assuming non-zero initial carry and denoted by C0). It is worth noting that the 8-bit prefix graph is a subset of Fig.5 and corresponds to the portion to the right of C8. Fig. 5 assumes availability of gi’s and pi ’s, where gi and pi are defined as xiyi and xi+yi, respectively. The small shaded circle in Fig. 3.1 represents the associative operation “0” and is defined as shown in

With reference to Fig. 3.1, the carry c1 is calculated as .c1=g0+p0co This can be written in terms of the

The calculation of carries of an 8-bit Ladner–Fischer adder therefore requires three stages (while four stages are required for a 16-bit Ladner–Fischer adder) excluding the stage that involves calculation of gi and pi The direct calculation of carry c1 = g0 + p0c0 requires two majority gates, namely one for AND operation and another for OR operation. We now present a new proposition that shows that c1 requires only one majority gate. Satisfy gipi = gi and gi =pi = pi. Similarly,(gi+1,pi+1 ) o ( gipi) is calculated as,

Using these results, we have the majority gate based representation for carry generation in an 8-bit Ladner–Fischer adder as shown in Fig. 6. Now we proceed to describe how the eight sums, denoted by si , I = 0,…,7 for an 8-bit Ladner–Fischer adder are generated. It is worth noting that the requirement for s0 can be duplicated for the remaining sum bits s1,…, s7. where the authors develop an expression for carry and sum in a one-bit full-adder as shown in (4). This requires three majority gates and two inverters.

To reduce the inverter requirements for sum si in particular, two relations as shown in (5) and (6) can be used. We omit the proof of the results in (5) and (6) since they directly follow from the definition of majority function for three Boolean variables.Considering the left half corresponding to generation of C16 to C9 to in Fig.6 we note that Stages 1, 2, and 3 involve four associative operations each. Each associative operation requires three majority gates. Hence, a total of 36 majority gates is required for these three stages. Stage 4 involves eight associative operations (that is, n/2, where n is 16).

B. 16-BIT HYBRID ADDER

Ladner–Fischer adder supports parallelism, the requirement of majority gates (which contributes to the overall area) is quite high. The large number of majority gates has an indirect effect on the wire (delay and amount). The proposed hybrid adder is based on the idea that a number of carries not explicitly labelled in Fig. 4.2 (in particular, c1 , c2 , c3 , c4 , c5 , c6 , c9 , c10 , c13 , c14.) highly efficient adder in terms of majority gates and delay. The majority gate requirement for carries c16 , c12 , c8 , and c4. With reference to fig. 6, we note that c16 , c12 , and c8 depend on , G3 , G2 , G1 and , respectively. Let , Gj , j = 1, 2, 3 represent the generate of (gi +3 ,pi +3) o (gi +2 ,pi +2) o (gi +1 ,pi +1) o (gi ,pi)where i= 4, 8, and 12, respectively. Gj Can be expanded as

Using , G3 , G2 , and G1, compute , c8 , c12 , and c16, as shown below equation respectively. It is to be emphasized that obtaining c8 (as also c12 and c16 ) this way using gi’s and pi’s provides for higher parallelism (when compared to a ripple carry adder). c8 , c12 , and c16, three other carries are computed in prefix style.

These are c7 , c11 , and c15, the equations shown above. For c7 , ten majority gates are required (including the requirements for pi’s and g4, majority gate for AND of p6 and p5, AND of p4 and c4 , AND of and p6 p5 and p4 c4 the OR operation).

PROPOSED METHODOLOGY

In proposed to describe about MAC, the circuit is operational to perform a operation and to perform a multiply operation without interfacing with the accumulate value of MAC operation using QCA. The circuit includes a first register, a second register, a multiplier circuit, and an accumulate circuit. The first register is addressable using either a primary first address or an alias second address. The circuit performs multiply operation to generate the product value based on data in the first and second register after a write operation to first register or second register. The MAC circuit must check for overflow, which might happen when the number of MAC operations is large. Overflow in a signed adder occurs when two operands with the same sign produce a result with a different sign.Fig. 8 shows the structure of the proposed MAC unit. The MAC unit consists of the multiplier and an accumulator unit. We first started implementing the multiplier, as it was the major portion of what we were planning to achieve. The multiplier array, that consist of multiplexers, half adders, full adders and the add cell (to add 0 or 1 to the LSB of the partial products)1. The carry save adder in the adder array is used here as it enables a very fast operation of the adding operation.

The accumulator performance can greatly increase the performance of the MAC unit. But the bottleneck for the accumulator is the multiplier unit. The accumulator must wait till it has correct logic values at its input for accumulation. The accumulator unit must comply with our initial objective of low power and high performance.

RESULTS AND DISCUSSIONS

In this paper, we have presented efficient QCA designs for the Ladner–Fischer prefix adder and a hybrid of Ladner–Fischer and the ripple carry adder. The designs are based on new results concerning majority logic. The hybrid adder is shown to be particularly well suited to the QCA model, it has better performance (in terms of latency) in QCA than a Ladner–Fischer or a ripple carry adder. And also show that the hybrid adder has a smaller area-delay product than existing adder designs in QCA. Area, power are Compared with prior work are presented and the detailed simulation results are also given.

The multiplier array, that consist of multiplexers, half adders, full adders and the add cell (to add 0 or 1 to the LSB of the partial products)1. The carry save adder in the adder array is used here as it enables a very fast operation of the adding operation. The accumulator performance can greatly increase the performance of the MAC unit. Shows that the hybrid adder has better performance (in terms of latency) in Quantum-dot cellular automata (QCA) than a Ladner–Fischer or a ripple carry adder.

ACKNOWLEDGMENTS

The authors would like to thank ,Dr.Mrs.S.Nirmala, Head Of The Department, Department of Electronics and Communication Engineering, Muthayammal Engineering College, for her stimulating comments, which helped me in bringing things in my way.We also acknowledge the Professors who collaborated with us for the design.

References

VikramkumarPudi and K. Sridharan, Senior Member, IEEE, Efficient Design of a Hybrid Adder in Quantum-Dot, IEEE Transactions on Very Large Scale Integration (VLSI) systems, vol. 19, no. 9, september 2011.

S. Srivastava, S. Sarkar, and S. Bhanja, “Estimation of upper bound of power dissipation in QCA circuits,” IEEE Trans. Nanotechnol., vol. 8, no. 1, pp. 116–127, Jan. 2009.

T. Dysart and P. M. Kogge, “Analyzing the inherent reliability of moderately sized magnetic and electrostatic QCA circuits via probabilistic transfer matrices,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 17, no. 4, pp. 507–516, Apr. 2009.

H. Cho and E. E. Swartzlander, “Adder and multiplier designs in quantum-dot cellular automata,” IEEE Trans. Comput., vol. 58, no. 6, pp. 721–727, Jun. 2009.

K. Kim, K. Wu, and R. Karri, “The robust QCA adder designs using composable QCA building blocks,” IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol. 26, no. 1, pp. 176–183, Jan. 2007.

S. Srivastava and S. Bhanja, “Hierarchical probabilistic macromodeling for QCA circuits,” IEEE Trans. Comput., vol. 56, no. 2, pp. 174– 190, Feb. 2007.

H. Cho and E. E. Swartzlander, “Adder designs and analyses for quantum-dot cellular automata,” IEEE Trans. Nanotechnol., vol. 6, no. 3, pp. 374–383, May 2007.

Hanninen and J. Takala, “Robust adders based on quantum-dot cellular automata,” in Proc. IEEE Int. Conf. Appl.-Specific Syst., Arch.Processors, 2007, pp. 391–396.

J. Huang, M. Momenzadeh, and F. Lombardi, “An overview of nanoscale devices and circuits,” IEEE Des. Test Comput., vol. 24, no. 4, pp. 304–311, Jul.–Aug. 2007.

K. Walus, T. Dysart, G. Jullien, and R. Budiman, “QCADesigner: A rapid design and simulation tool for quantum-dot cellular automata,”IEEE Trans. Nanotechnol., vol. 3, no. 1, pp. 26–29, Jan. 2004.