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Advanced Pipelined Area and Speed Efficient Floating-Point ALU Embedded System in FPGA

Abstract

This paper introduces a technique to style and develop a completely pipelined and optimized design for Floating Point embedded processor in FPGA exploitation IEEE 754 format. The Floating purpose embedded processor performs many operations such as FP-Arithmetic, FP-Logical, FP-Trigonometric, FP-Vector, FP-Complex, FP-Signed, FP-Unsigned. In an exceedingly existing system, a fixed point illustration which give terribly restricted vary and a hard and fast point illustration having the shortcoming to represent a third values. At first separate floating purpose unit design is employed for arithmetic operation. However during this paper Embedded Processor itself performing the many operations in a same processor itself. Floating purpose Embedded Processor having the benefits as giant dynamic varies, less development time and a fewer cycles to execute than a mounted purpose. Floating purpose processors a lot of easier to program in assembly code. Floating purpose operations need a large amount of FPGA resources. The design is meant and then improvement is completed. Improvement shows that they need the advantages of improved space, area-delay product, and outturn. This paper implements AN economical floating purpose operation according to IEEE 754 normal with optimum chip space and high performance exploitation VHDL. The planned style has optimized the complex parts to reach higher overall implementation. Scope of this paper is enforced in real time computations and Floating purpose ALU designed with FPGA offers low price with high economical results.

A.Lakshminarayanan, N.Jayapal, K.Kumar,V.Krishnakumar ,K.Shajudeen

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