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An Efficient Design of Fully Fault Tolerant Communication by FSD-ECC with Low Power Consumption and More Security

Abstract

This paper presents “an advanced fully fault tolerant communication by FSD-ECC with low power consumption and more security” To prevent soft errors from causing data corruption, memories are typically protected with error correction codes. An advanced error correction codes are used when an additional protection is needed. a fully fault-tolerant memory architecture that is capable of tolerating hardware or software errors not only in the memory bits but also in the supporting logic including the ECC encoder and corrector with low power consumption and more security. This project uses a Euclidean Geometry codes, SEA (Scalable Encryprion Algorithm). Hence proved that these codes are part of a new subset of ECCs that have FSD(fault secure detector - error correcting code).This is useful as majority logic decoding can be implemented serially with simple hardware but requires a large decoding time. For memory applications, this increases the memory access time. The method detects whether a word has errors in the first iterations of majority logic decoding, and when there are no errors the decoding ends without completing the rest of the iterations. Since most words in a memory will be error-free, the average decoding time is greatly reduced. In this brief, we study the application of a similar technique to a class of Euclidean geometry low density parity check (EGLDPC) codes that are one step majority logic decodable. The results obtained show that the method is also effective for EG-LDPC codes. Other than this LDPC codes satisfies a new, restricted definition for ECCs which guarantees that the ECC codeword has an appropriate redundancy structure such that. it can detect multiple errors occurring in both the stored codeword in memory and the surrounding circuitries. which makes the area overhead minimal and keeps the extra power consumption low. Extensive simulation results are given to accurately estimate the probability of error detection for different code sizes

B. Sai Bhargavi, P. Praveen Kumar

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