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An Efficient VLSI Architecture for Primary Synchronization Signal Detector

Abstract

In this paper, we present a novel design for the detection of primary synchronization signal in a Long Term Evolution (LTE) system based device at the expense of low cost and low power. This is facilitated by using a matched filter architecture which incorporates parallel processing. The approach of a 1-bit analog-to-digital converter (ADC) with down-sampling is compared with that of a 10-bit ADC without down-sampling under multi-path fading conditions defined in LTE standard for user equipment (UE) performance test. A high performance primary synchronization signal detection method is derived in this paper.

Mathana.J.M, Ashvanth.R, Bhavanam Jagadish, Ashok Robert.J

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