Research Article Open Access

Cache Controller with Enhanced Features using Verilog HDL

Abstract

The major role of cache controller is reduction in the data transfer access time between the CPU and cache. The fact that read request is more critical compared to write request is exploited in this paper. The paper presents a novel approach to cache controllers which uses read write partitioning wherein more read lines are maintained as compared to write lines.

Prof. V. B. Baru, Sweety Pinjani

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