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Design and implementation of Deadlock Avoidance for On Chip Buses with Elastic
Buffer and Error Correction
Abstract
Advanced extensible interface protocol and open core protocol are protocols used for on chip
communication it can support advanced transactions and it also improve communication efficiency. Out-of-order
transactions are return responses in an order different from requested ones. Here we discuss a concept it can support out
of order transactions. A graphical model used in the system known as bus status graph used to identify the occurrence
of dead lock condition. According to this graphical model we propose a technique it can avoid this deadlock problem.
And also using an error detection and correction method to avoid the mismatches in read and write operation between
master and slave.