Research Article Open Access

FPGA IMPLEMENTATION OF DIGITAL PLL FOR MAINTAINING SPEED OF DC MOTOR

Abstract

The digital PLL has ability to overcome the drawbacks and performance issues arriving in other controller like fuzzy logic controller, analog PLL and PID controller. So the implementation of digital phase locked loop (DPLL) controller is considering for DC motor speed control. The main emphasis is on the FPGA (Field Programmable Gate Array) implementation of the digital PLL and PWM generator. Digital PLL offer a highly stable frequency controlling than other controller like analog PLL, PID and fuzzy logic controller. The closed loop sensing element is an optical encoder, which outputs an impulse train with a frequency proportional to the motor rotational speed. This impulse train will be synchronized by the Digital PLL to a reference impulse train of a given precise frequency generated inside the FPGA from a quartz crystal oscillator. The phase difference between the two impulse trains is measured by a phase detector by counting pulse width of both the impulses. The phase detector converts the phase difference to a numerical value that can be processed digitally by the loop filter. The loop filter acts as a regulator.DCO (Digital Controlled Oscillator) block of this PLL is replaced by a combination set of Motor and encoder. The DC motor terminal voltages controlled using MOSFET based chopper circuit. The chopper is driven by a précised frequency PWM signal. The result of the project shows that motor speed is not affected so much with the varying loads. On loading the motor speed slow down for about 40 rpm (10%) of its normal speed 400rpm, on unloading the motor speed is hunting to its normal speed 400 rpm. The motor used in this experiment is a DC motor with rated speed of 500 rpm and rated voltage of 12 Volt and rated current of 1 Ampere. Results show the behavior of the designed digital PLL and PWM generator circuits in FPGA.

Bhaskar P.C.1 and Gupta D. K

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