Research Article Open Access

High Performance and Low Power VLSI Synchronous Systems Using an Explicit Pulsed Dual Edge Triggered Flip Flops

Abstract

An explicit pulsed dual edge triggered sense amplifier flip flops (DET-FF).In this dual edge triggered sense amplifier flip flop is used for low–power consumption and high performance application. By incorporating the dual edge triggering mechanism, the dual edge triggered flip flop is able to achieve low power consumption that has minimum delay. Clock gating is a popular technique used in many synchronous circuits; hence, the power dissipation is very much reduced. Reducing dynamic power reduction. Clock gating saves power by adding more logic gates in the circuit. It can be used in various applications like digital VLSI clocking system, buffers, registers, microprocessors etc.

R.Ramya,V.Saranya1,Y.Vivekananth

To read the full article Download Full Article | Visit Full Article