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Low Power, Area Efficient & High Performance Carry Select Adder on FPGA

Abstract

LOW-POWER, area-efficient, and high-performance VLSI systems are increasingly used in portable and mobile devices, multi standard wireless receivers, and biomedical instrumentation. An adder is the main component of an arithmetic unit. A complex digital signal processing (DSP) system involves several adders. An efficient adder design essentially improves the performance of a complex DSP system. A ripple carry adder (RCA) uses a simple design, but carry propagation delay (CPD) is the main concern in this adder. Carry look-ahead and carry select (CS) methods have been suggested to reduce the CPD of adders. A conventional carry select adder (CSLA) is an RCA configuration that generates a pair of sum words and output carry bits corresponding the anticipated input-carry (cin = 0 and 1) and selects one out of each pair for final-sum and final output-carry . A conventional CSLA has less CPD than an RCA, but the design is not attractive since it uses a dual RCA. In the existing designs, logic is optimized without giving any consideration to the data dependence. In this paper, we prepared an analysis on logic operations occupied in conventional and BEC-based CSLAs to study the data dependence and to identify redundant logic operations. Based on this study, we have planned a new logic formulation for the CSLA. The major contribution in this paper is logic formulation based on data dependence and optimized carry generator (CG) and carry select unit Based on the proposed logic formulation, we have found a capable logic design for CSLA. Due to better logic units, the projected CSLA involves significantly less ADP than the existing CSLAs. We have shown that the SQRT-CSLA using the proposed CSLA design involves nearly 32% less ADP than that of the corresponding SQRT-CSLA.

Bagya Sree Auvla, R.Kalyan

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