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Pipelined Floating Point Multiplier Based On Vedic Multiplication Technique

Abstract

To represent very large or small values, large range is required as the integer representation is no longer appropriate. These values can be represented using the IEEE 754 standard based floating point representation. Multiplying floating point numbers is a critical requirement for DSP applications involving large dynamic range. The paper describes the implementation and design of IEEE 754 Pipelined Floating Point Multiplier based on Vedic Multiplication Technique. The inputs to the multiplier are provided in IEEE 754, 32 bit format. The Urdhva Triyakbhyam sutra is used for the multiplication of mantissa. The underflow and overflow cases are handled.

Irine Padma B.T, Suchitra. K

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