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Study and Analysis of Full Adder in Different Sub-Micron Technologies with an Area Efficient Layout of 4-Bit Ripple Carry Adder

Abstract

In electronics, adder is an obligatory component of every single integrated circuit. Adder is primary fast and secondly consumed less power and also chip area. We define various adders to perform addition method in VLSI technology. Full adder designing with respect to low power is becoming more popular now adays. It is an essential components of every ALU block. To perform fast arithmetic operations, ripple carry adder is one of the fastest adders used in many data- processing processors. In this paper we analysed a full adder circuit in different sub-micron technologies and obtain low power and minimum delay of it. We also design area efficient layout of full adder schematic. With the help of full adder low power with delay consumed model we design a ripple carry adder schematic and make an area efficient layout of it[1].

Sayan Chatterjee

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