Research Article Open Access

System Level Tools for Designing FIR Filter on FPGA

Abstract

In this paper, Design of FIR Filter using System Level Tools like Simulink in Xilinx System Generator and hardware based FIR Filter Design using Verilog has been proposed. System level tools like Xilinx System Generator are used to design an efficient DSP Algorithms and Applications on FPGA. Both the designs have been further synthesized on Xilinx Spartan3 FPGA kit. Finally, a comparison is done between the results obtained from the software simulations and those from FPGA

Mrs.Bhagyalakshmi N, Dr.Rekha K R , Dr.Nataraj K R

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